Integrated circuits contain a variety of structures made of different materials. The sensitivity of the structures to stress rises sharply due to the structure sizes that are gradually becoming smaller.
Electrostatic discharges (ESD) in and/or through the chip are one type of stress. These arise due to charge separation and charge collection, if two surfaces of materials having different electron affinities touch. An electrostatic charge already arises if a small component slips from a machine or a package.
Such an electrostatic charge charges components up to several thousands of volts. Defects on components and structures in modern ASICs may already occur from >1 V depending on the technology.
Electrostatic discharges occur comparatively frequently. To nonetheless enable the manufacturing and/or the processing of the chips, structures are incorporated into ASICs, which clamp the voltage at the input of the IC.
So-called ESD clamps offer a low-ohmic path to the accumulated charge, in order to dissipate the charge carriers. The sensitive structures of the ASICs are thus protected from high voltages and currents.
Despite these ESD clamps, an electrostatic discharge means stress for an ASIC. ESD clamps are thus dimensioned as cost-effectively as possible, because they already require a comparatively large surface area when cost-effectively dimensioned, for example, depending on the strength of the ESD, up to 30% of the total circuit size. For this reason, some ESD structures only withstand a limited number of discharges and subsequently may no longer sufficiently protect the ASIC. Moreover, the ESD clamps are dimensioned in such a way that the ASIC is only protected from an overvoltage within the scope of its specification. An unexpectedly high voltage which is briefly applied to the ASIC may thus nonetheless destroy components.
The staff of the failure analysis department are often only left with the option of suspecting electrical overstress (EOS).
The document by F. Altolaguirre and M. Ker (2013), “Power-Rail ESD Clamp Circuit With Diode-String ESD Detection to Overcome the Gate Leakage Current in a 40-nm CMOS Process,” IEEE Transactions on Electron Devices, vol. 60, issue 10, pp. 3500-3507, describes the recognition of an electrostatic discharge to be able to activate a discharge protection circuit in the event of a discharge having a lower startup current. A discharge protection circuit is actually connected in such a way that this special circuit operates more efficiently.
The document by M. Ker et al. (2010), “On-Chip ESD Detection Circuit for System-Level ESD Protection Design,” 10th IEEE Conference on Solid-State and Integrated Circuit Technology ICSICT, pp. 1584-1587, discusses an ESD event or a transient signal which is detected during operation, to bring the circuit of a TFT-LC display into a safe state.
The document by H. Sung et al. (2010), “Design of Toroidal Current Probe Embedded in Multilayer Printed Circuit Boards for Electrostatic Discharge ESD Detection,” IEEE Electrical Design of Advanced Package and Systems Symposium, pp. 1-4, discusses that an ESD event may be detected with the aid of an integrated electrical coil. This is confirmed by a measurement using a current measuring clamp meter.
The document by W. Kuhn and R. Eatinger (2011), “BUILT-IN SELF-TEST IN INTEGRATED CIRCUITS—ESD EVENT MITIGATION AND DETECTION”, Master's Thesis at Kansas State University 2011, discusses the detection of an ESD event or a transient signal during the operation by fusion of a type of fuse. This is because a thin line, which is destroyed under ESD stress, is connected in parallel to the ESD coupling diodes. This destruction is a stored piece of information. A function cannot be guaranteed under all conditions, however. The destruction may negatively affect the ASIC.
It may be disadvantageous that the method may not be reliable. It may detect a discharge, but not count it. The ASIC may thus be damaged. The detection is not reversible and a large surface area is required on the chip.